Yayınlar & Eserler

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SCI-E, SSCI, AHCI (4)
SCI-E, SSCI, AHCI, ESCI (4)
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Hakemli Bilimsel Toplantılarda Yayımlanmış Bildiriler 18

1. On the Complexity of Timed Pattern Matching

19th International Conference on Formal Modeling and Analysis of Timed Systems, FORMATS 2021, Virtual, Online, 24 - 26 Ağustos 2021, cilt.12860 LNCS, ss.15-31, (Tam Metin Bildiri)

2. Reactive Control Meets Runtime Verification: A Case Study of Navigation

19th International Conference on Runtime Verification, RV 2019 held as part of the 3rd World Congress on Formal Methods, FM 2019, Porto, Portekiz, 8 - 11 Ekim 2019, cilt.11757 LNCS, ss.368-374, (Tam Metin Bildiri) Creative Commons License

3. Timescales: A Benchmark Generator for MTL Monitoring Tools

19th International Conference on Runtime Verification, RV 2019 held as part of the 3rd World Congress on Formal Methods, FM 2019, Porto, Portekiz, 8 - 11 Ekim 2019, cilt.11757 LNCS, ss.402-412, (Tam Metin Bildiri)

4. Special Session: Embedded Software for Robotics: Challenges and Future Directions

18th ACM SIGBED International Conference on Embedded Software, EMSOFT 2018, Turin, İtalya, 30 Eylül - 05 Ekim 2018, (Tam Metin Bildiri)

5. DejaVu: A monitoring tool for first-order temporal logic

3rd Workshop on Monitoring and Testing of Cyber-Physical Systems, MT-CPS 2018, Porto, Portekiz, 10 Nisan 2018, ss.12-13, (Tam Metin Bildiri)

6. Specifying timed patterns using temporal logic

21st International Conference on Hybrid Systems: Computation and Control, HSCC 2018, Porto, Portekiz, 11 - 13 Nisan 2018, ss.167-176, (Tam Metin Bildiri)

7. AMT 2.0: Qualitative and quantitative trace analysis with extended signal temporal logic

24th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, TACAS 2018 Held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2018, Thessaloniki, Yunanistan, 14 - 20 Nisan 2018, cilt.10806 LNCS, ss.303-319, (Tam Metin Bildiri)

8. First order temporal logic monitoring with BDDs

17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017, Vienna, Avusturya, 2 - 06 Ekim 2017, ss.116-123, (Tam Metin Bildiri)

9. Combining the temporal and epistemic dimensions for MTL monitoring

15th International Conference on Formal Modelling and Analysis of Timed Systems, FORMATS 2017, Berlin, Almanya, 5 - 07 Eylül 2017, cilt.10419 LNCS, ss.207-223, (Tam Metin Bildiri)

10. On the quantitative semantics of regular expressions over real-valued signals

15th International Conference on Formal Modelling and Analysis of Timed Systems, FORMATS 2017, Berlin, Almanya, 5 - 07 Eylül 2017, cilt.10419 LNCS, ss.189-206, (Tam Metin Bildiri)

11. Montre: A tool for monitoring timed regular expressions

29th International Conference on Computer Aided Verification, CAV 2017, Heidelberg, Almanya, 24 - 28 Temmuz 2017, cilt.10426 LNCS, ss.329-335, (Tam Metin Bildiri) Creative Commons License

12. Online timed pattern matching using derivatives

22nd International Conference on Tools and Algorithms for the Construction and Analysis of Systems, TACAS 2016 and held as Part of the European Joint Conferences on Theory and Practice of Software, ETAPS 2016, Eindhoven, Hollanda, 2 - 08 Nisan 2016, cilt.9636, ss.736-751, (Tam Metin Bildiri)

13. Measuring with timed patterns

27th International Conference on Computer Aided Verification, CAV 2015, California, Amerika Birleşik Devletleri, 18 - 24 Temmuz 2015, cilt.9207, ss.322-337, (Tam Metin Bildiri)

14. Integrating circuit analyses for assertion-based verification of programmable AMS circuits

Forum on Specification and Design Languages, FDL 2013, Paris, Fransa, 01 Eylül 2013, cilt.311 LNEE, ss.67-84, (Tam Metin Bildiri)

15. Timed pattern matching

12th International Conference on Formal Modeling and Analysis of Timed Systems, FORMATS 2014, Florence, İtalya, 8 - 10 Eylül 2014, cilt.8711 LNCS, ss.222-236, (Tam Metin Bildiri)

16. Integrating circuit analyses for assertion-based verification of programmable AMS circuits

2013 16th Forum on Specification and Design Languages, FDL 2013, Paris, Fransa, 24 - 26 Eylül 2013, (Tam Metin Bildiri)

17. Analog layer extensions for analog/mixed-signal assertion languages

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013, İstanbul, Türkiye, 7 - 09 Ekim 2013, ss.66-71, (Tam Metin Bildiri)

18. Using haloes in mixed-signal assertion based verification

2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012, Huntington Beach, CA, Amerika Birleşik Devletleri, 9 - 10 Kasım 2012, ss.49-55, (Tam Metin Bildiri)
Metrikler

Yayın

22

Yayın (Scopus)

22

Atıf (Scopus)

370

H-İndeks (Scopus)

11

Tez Danışmanlığı

1

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4