A 0.65-1.35 GHz synthesizable all-digital phase locked loop with quantization noise suppressing time-to-digital converter

Balcioǧlu Y., DÜNDAR G.

Turkish Journal of Electrical Engineering and Computer Sciences, cilt.25, sa.3, ss.2410-2423, 2017 (SCI-Expanded, Scopus, TRDizin) identifier identifier

  • Yayın Türü: Makale / Tam Makale
  • Cilt numarası: 25 Sayı: 3
  • Basım Tarihi: 2017
  • Doi Numarası: 10.3906/elk-1601-185
  • Dergi Adı: Turkish Journal of Electrical Engineering and Computer Sciences
  • Derginin Tarandığı İndeksler: Science Citation Index Expanded (SCI-EXPANDED), Scopus, TR DİZİN (ULAKBİM)
  • Sayfa Sayıları: ss.2410-2423
  • Anahtar Kelimeler: All-digital phase-locked loop, Digitally controlled oscillator, Quantization noise suppression, Time-to-digital converter
  • Boğaziçi Üniversitesi Adresli: Evet

Özet

This paper presents a new quantization noise suppression method for a time-to-digital converter (TDC) and proposes an all-digital phase-locked loop (ADPLL) architecture using only standard cell logic gates. Using a new multiple input multiple output (MIMO) quantization noise suppression method provides an order of √2N improvement in TDC resolution with N parallel TDC channels. Suppressed noise in the TDC allows the ADPLL to achieve superior jitter performance in both theoretical calculations and simulation results. In order to allow fast portability between process nodes, short design cycle time, ease of modification, and exibility, ADPLL architecture is designed completely in register transfer level intensive Verilog code and the implementation is synthesized in order to obtain final microelectronic design schematics. In comparison to similar work in the literature, postlayout simulation results show that the designed ADPLL achieves period jitter of 1.78 psrms with a layout area of 0.09 mm2 in 65 nm CMOS process and power consumption of 17.5 mW at 800 MHz.