MVBLA based design of constrained 1-bit transform based motion estimation algorithm Kisitlanmiş 1-bit dönü̧ümü temelli hareket kestirimi algoritmasinin HVTDD yaklaşimiyla tasarimi

ÇELEBİ A., URHAN O., ERTÜRK S., Hamzaoǧlu I., DÜNDAR G.

2008 IEEE 16th Signal Processing, Communication and Applications Conference, SIU, Aydın, Türkiye, 20 - 22 Nisan 2008, (Tam Metin Bildiri) identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Doi Numarası: 10.1109/siu.2008.4632681
  • Basıldığı Şehir: Aydın
  • Basıldığı Ülke: Türkiye
  • Boğaziçi Üniversitesi Adresli: Evet

Özet

In this work a novel hardware proposed for Constrained 1-bit Transform based motion estimation to facilitate real time operation. The designed system occupies a small area in a general purpose FPGA fabric and it is therefore efficient to implement a whole video coding architecture on a single FPGA chip. The designed system can perform ME operation for a 2048 x1152 pixel sized image frame at a speed of 20 frames/second. ©2008 IEEE.