Implementation of a radix 2n multiplier using high performance logic

Ozev S., Altinordu A., DÜNDAR G.

Proceedings of the 1996 8th Mediterranean Electrotechnical Conference, MELECON'06. Part 3 (of 3), Bari, İtalya, 13 - 16 Mayıs 1996, cilt.1, ss.469-472, (Tam Metin Bildiri) identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Cilt numarası: 1
  • Basıldığı Şehir: Bari
  • Basıldığı Ülke: İtalya
  • Sayfa Sayıları: ss.469-472
  • Boğaziçi Üniversitesi Adresli: Evet

Özet

In this study, a 16 × 16 bit radix 2n multiplier was implemented using high performance logic. The design was done in a bottom-up style, where the performance of each block in the corresponding hierarchy was optimized starting from the transistor level. The performance of the radix 2n multiplier was compared with some existing multipliers.