Comparison of QMC-based yield-aware pareto front techniques for multi-objective robust analog synthesis

Pak M., Fernandez F. V., DÜNDAR G.

Integration, the VLSI Journal, cilt.55, ss.357-365, 2016 (SCI-Expanded, Scopus) identifier identifier

  • Yayın Türü: Makale / Tam Makale
  • Cilt numarası: 55
  • Basım Tarihi: 2016
  • Doi Numarası: 10.1016/j.vlsi.2016.04.004
  • Dergi Adı: Integration, the VLSI Journal
  • Derginin Tarandığı İndeksler: Science Citation Index Expanded (SCI-EXPANDED), Scopus
  • Sayfa Sayıları: ss.357-365
  • Anahtar Kelimeler: Analog design automation, Multi-objective optimization, Robust synthesis, Yield-aware optimization
  • Boğaziçi Üniversitesi Adresli: Evet

Özet

This paper focuses on the implementation of different techniques for the integration of yield estimation in the synthesis loop of analog integrated circuits (ICs). MOEA/D (Multi-Objective Evolutionary Algorithm with Decomposition) is considered to be a very powerful multi-objective optimization algorithm. For the consideration of yield, several techniques are discussed and three different yield-aware Pareto front (PF) generation techniques have been implemented on the MOEA/D optimizer. The implemented yield-aware PF techniques are compared by designing a fully-differential folded-cascode amplifier with different number of objectives. In order to embed the variation effects into the optimization loop, the statistical analysis of the circuit has been carried out by using a Quasi Monte Carlo (QMC) technique. The results suggest that especially two of these techniques look promising for high dimensional robust optimization of analog circuits.