2008 4th IEEE International Conference on Circuits and Systems for Communications, ICCSC, Shanghai, Çin, 26 - 28 Mayıs 2008, ss.307-311, (Tam Metin Bildiri)
In this paper, a minimum mean-squared-error (MMSE) equalizer design algorithm is proposed for low power and hardware efficient implementation. The power/hardware efficiency is directly related to the total number of non-zero digits in the equalizer coefficients in their binary representation. The proposed method thus searches among the equalizer coefficients with the smallest number of non-zero digits while attaining a MSE that is less than or equal to that of the equalizer implemented with rounded coefficients. This not only assures that there is no respective performance loss but also provides a reduction of 18% in the number of non-zero bits, as shown by the numerical examples. ©2008 IEEE.