Akademik Veri Yönetim Sistemi
13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015, Grenoble, Fransa, 7 - 10 Haziran 2015, (Tam Metin Bildiri)
A 7 ps/LSB, 0.02 mm2 and 3.9 mW@50MHz Time to Digital Converter architecture with novel MIMO spatial oversampling method is proposed as part of an effort to implement an all-digital PLL (ADPLL) by replacing the phase frequency detector in phase locked loops (PLL). Multiple ring oscillators with unique and variable frequencies are used in order to make N independent measurements of the time pulse to be measured M times in order to create transmitter and receiver diversity similar to those in MxN MIMO antenna arrays. Targeted for wired applications, the design favors portability and flexibility by using standard cells and digital design flow.