Akademik Veri Yönetim Sistemi
2010 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2010, Athens, Yunanistan, 12 - 15 Aralık 2010, ss.239-242, (Tam Metin Bildiri)
Random Number Generators with logic gates only are popular among digital IC designers in terms of their speed compatibility and uncomplicated integration to digital platforms. To the best of our knowledge, this paper presents the first ASIC implementation of a Random Number Generator based on Fibonacci and Galois ring oscillators. Prototypes have been designed and fabricated by using HHNEC's 0.25μm eFlash process with a supply voltage of 2.5V. Fibonacci and Galois ring oscillators are implemented in combined configuration. A combined configuration, which consists of a Fibonacci ring oscillator with 16 inverters and a Galois ring oscillator with 32 inverters, occupies 0.0048mm2 and dissipates 2.5mW of power which is quite small compared to other well-known random number generators based on digital circuitry. IC design level experiences, measurements, analysis of measurements and statistical test results are also demonstrated. Furthermore, we propose to use several of these oscillators in an xored configuration, in order to speed up and improve the quality of the generated bit stream. We could achieve fulfilled test results from NIST 800-22 test suit after Von Neumann corrector for 7 xored Fibonacci and Galois ring oscillators with a sampling frequency of 125M Hz and 31.25Mbps throughput. In addition, increasing the number of xored Fibonacci and Galois ring oscillators from 7 to 8 also fulfills the tests of NIST 800-22 at the same sampling frequency however, without any further post processing. T hus, 125Mbps of throughput, which is the highest data rate to date with fulfilled test results, could be obtained. ©2010 IEEE.