Akademik Veri Yönetim Sistemi
23rd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte-Carlo, Monako, 11 - 14 Aralık 2016, ss.133-136, (Tam Metin Bildiri)
This paper presents a new approach to hierarchically synthesize analog circuits. In general, behavioral models are preferred at intermediate levels to reduce total synthesis time. However, there are problems associated with the usage of behavioral models such as significantly sacrificing the accuracy and costly preparation time for model generation. Therefore, a model-free approach is proposed, in which behavioral models are eliminated at higher level. Top level specifications and sub-block performances are optimized simultaneously during the synthesis process, where performance requirements of sub-blocks are arranged automatically. A third order low pass Butterworth filter is used as an example to show the effectiveness of the proposed approach.