Implementation of constrained 1-bit transform based motion estimation algorithm with an FPGA based architecture Kisitlanmiš 1-bit dönüşümü temelli hareket kestirimi algoritmasinin FPGA tabanli bir mimari ile gerçeklenmesi

ÇELEBİ A., URHAN O., ERTÜRK S., DÜNDAR G.

2007 IEEE 15th Signal Processing and Communications Applications, SIU, Eskişehir, Türkiye, 11 - 13 Haziran 2007, (Tam Metin Bildiri) identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Doi Numarası: 10.1109/siu.2007.4298727
  • Basıldığı Şehir: Eskişehir
  • Basıldığı Ülke: Türkiye
  • Boğaziçi Üniversitesi Adresli: Evet

Özet

In this work a novel FPGA based hardware is proposed to implement the Constrained One-Bit Transform based block motion estimation algorithm to facilitate real time operation. The designed system occupies a small area in a general purpose FPGA fabric and, that is why it is efficient to implement a whole video coding architecture on a single ASIC chip or an FPGA. The designed system can perform the motion estimation task for a 352×288 pixel sized image frame at a speed of 50 frames/second. The designed hardware can further be multiplexed to increase the parallelism for a real time operation for higher image frame sizes, e.g. for HDTV applications.