All-digital phase locked loop design assistant

Balcioglu Y., DÜNDAR G.

International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2015, İstanbul, Türkiye, 7 - 09 Eylül 2015, (Tam Metin Bildiri) identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Doi Numarası: 10.1109/smacd.2015.7301710
  • Basıldığı Şehir: İstanbul
  • Basıldığı Ülke: Türkiye
  • Anahtar Kelimeler: ADPLL, Automation, CAD, High-Level Synthesis
  • Boğaziçi Üniversitesi Adresli: Evet

Özet

An All-Digital Integer-N Phase Locked Loop (ADPLL) design assistant that models all the sub-blocks and noise sources in phase domain has been developed. For chosen top level design parameters, the generator designs the desired closed loop, open loop and digital loop filter characteristics of the ADPLL and analyzes the resulting phase noise performance of the loop.