A 7.3 ¿w decimation filter for 15 bit 25 kHz audio ¿¿ modulator

Ince M., Akcakaya F. M., DÜNDAR G.

2014 IEEE Faible Tension Faible Consommation, FTFC 2014, Monaco, Monako, 4 - 06 Mayıs 2014, (Tam Metin Bildiri) identifier

  • Yayın Türü: Bildiri / Tam Metin Bildiri
  • Doi Numarası: 10.1109/ftfc.2014.6828601
  • Basıldığı Şehir: Monaco
  • Basıldığı Ülke: Monako
  • Anahtar Kelimeler: decimation, filter, low power, sigma-delta
  • Boğaziçi Üniversitesi Adresli: Evet

Özet

This paper presents a low power decimation filter designed for oversampling ¿¿ Analog to Digital Converters (ADC). The Decimation filter consists of three stages; namely, CIC filter, Half-Band filter, and FIR filter. In order to reduce power, Canonical Signed Digit (CSD) representation, multiplierless filter architecture, polyphase structure, and multistage CIC structure are utilized. In addition, Finite Impulse Response (FIR) is designed using the GAM algorithm. The proposed filter is synthesized with CMOS 0.18¿m technology. It consumes 7.25 ¿W for 15 bit Audio ¿¿ Modulator with sampling frequency of 1.6 MHz and 25 kHz bandwidth. © 2014 IEEE.