Akademik Veri Yönetim Sistemi
14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2017, Giardini Naxos, Taormina, İtalya, 12 - 15 Haziran 2017, (Tam Metin Bildiri)
In modern CMOS technology, local electrical stress has substantially increased as device geometries scaled down more aggressively compared to supply voltages. As a result, time-dependent degradation mechanisms (aging phenomena) became an important performance problem, which leads to a considerable lifetime reduction in manufactured integrated circuits. Combination of these aging phenomena with process variations has made reliability a major design objective. In analog circuits, different approaches have been proposed to mitigate the performance challenges related to device reliability. This paper discusses aging in CMOS technology and reviews reliability-aware analog circuit design methodologies for nanoscale circuits.