Akademik Veri Yönetim Sistemi
19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2016, Koshice, Slovakya, 20 - 22 Nisan 2016, (Tam Metin Bildiri)
This study presents a parasitic-aware RF circuit synthesis tool, in which layout-induced parasitics of passive devices are captured by using sophisticated equivalent models for them. Recently, analog circuit design has been fully automated, where a circuit sizing is followed by a layout generator. However, there is often a discrepancy between synthesis and post-layout results, especially for RF applications, due to severe layout-induced parasitics of passive devices. Therefore, a number of iterations between circuit sizing and layout generator are required to achieve a fully satisfactory solution, which lead to dramatically increased synthesis times. The proposed approach provides more realistic results at the sizing part via optimizing physical parameters of passive devices, rather than their electrical values, thus, iteration count between circuit sizing and layout generation can be kept at a minimum.